06 Timing

Circuit Design Attributes

• Area
• Speed
• Energy Consumption
• Design Time

Timing:

• How fast is a circuit?
• How can we make a circuit faster?
• What happens if we run a circuit too fast?

Delay is caused by (physics):

• capacitance and resistance
• finite speed of light

Delay is affected by:

• rising vs falling
• different inputs
• environment (humidity)
• aging
• voltage

Types of Delay

Longest, Shortest Delay Path

Remember though that even wires can affect the delay, increasing with length

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Implementation Comparisons

Ouput Glitches

Let’s say I calculated a delay wrong and therefore latch some wrong result at clock edge.

Definition Glitch

One input transition causes multiple output transitions

On the left we initially have 0, 1, 1 input. So the top AND gate initially outputs 0. The bottom AND gate outputs 1. The final OR gate outputs 1.

Now, suppose the middle input 1 → 0:

1. bottom AND gate becomes 0
2. top AND gate is slower, still outputs 0
3. final OR output is 0
4. Slow Path catches up (ouput turns back to 1)

Not too important, timing analysis is important, but we don’t always care about glitches.

How to avoid Glitches

→ see 07 K-Maps

Sequential Circuit Timing, D Flip-Flop

Metastability: Things changed while the sampling

$t_{ccq}$: Shortest Delay $t_{pcq}$: Worst case delay

Sequential Timing

Ensuring Correct Sequential Operation

Delay types

Success

The clock cycle time $T_c$ needs to be greater than the sum of

1. maximum delay of reading the data from R1 (propagation delay from clock to q, $t_{pcq}$). At that point Q1 is stable.
2. maximum delay of the combinational logic CL ($t_{pd}$)
3. the maximum time D2 needs to stay stable ($t_{\text{setup}}$)

• $t_{pcq}$ is the upper bound (propagation delay clock to q)
• $t_{ccq}$ is the lower bound (contamination delay) of the time from the rising edge of the clock until the output changes.
• the setup and hold times indicate when the inputs must be stable relative to the rising edge of the clock

Setup contraint

An asynchronous design would not have this overhead, but barely possible to design.

Critical path: path with the longest $t_{pd}$.

• critical path too long: slow
• critical path too short: each cycle will do very little useful work

Hold Time Constraint

Example: Timing Analysis

This circuit won’t work because we don't satisfy the hold time constraints.

$t_{pd}$ is always calculated using the critical path.

To fix the hold time, add buffers. The critical path is not affected as can be seen, and the added contamination delay fixes the hold time constraints.

Clock Skew

Clocks have delays too. Clock Skew is the time difference between two clock edges. So different registers can have shifted f.ex. rising edges of the clocks.

This increases Setup and Hold time.

Clock Skew: Setup Time

Clock Skew: Hold Time

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