03 Storage

Two inverters connected in a loop. There are two different options for this, so we can store one bit. It is stable. $Q=0,\overline{Q}=1\text{or}Q=1,\overline{Q}=0$

Problem is this runs forever, so we need a control mechanism. We get our desired value to bitline. Raising the wordline to 1 allows for data to flow in our out. At wordline = 0 the SRAM loop holds state indefinitely.

Storage Types

The Reset-Set Latch

Problem: The forbidden state S = R = 1 is ambiguous and must be avoided.

Gated D Latch

To avoid setting R and S to 0 at the same time (forbidden). Only has one input.

Left side takes Dand write enable and creates S and R: $S=\overline{D\cdot WE}R=\overline{\overline{D}\cdot WE}$ S and R can never be 0 at the same time because $\overline{D}$ and $D$ can’t be 0 at the same time.

• write enable = 0, dann haben die beiden linken NAND’s ouput 1, unabhängig von D. damit haben wir $S=1,R=1$, und das System ist idle, holding $Q_{\text{prev}}$.
• write enable = 1, dann
  • Wenn D=0, dann $S=1,R=0$, somit Q=0
  • Wenn D=1, dann $S=0,R=1$, somit Q=1
  • in beiden Fällen hat Q den Wert von D

D Flip-Flop

Success

Changes only happen on rising edge.

Multiple D Flip-Flops:

Register

• a combination of flip-flops that share a common CLK input
• all bits of the register are updated at the same time